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| Features * High Performance, Low Power AVR (R) 8-bit Microcontroller * Advanced RISC Architecture - 131 Powerful Instructions - Most Single Clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 1 MIPS throughput per MHz - On-chip 2-cycle Multiplier Data and Non-Volatile Program Memory - 16K/32K/64K Bytes Flash of In-System Programmable Program Memory * Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits - In-System Programming by On-chip Boot Program * True Read-While-Write Operation - 512/1024/2048 Bytes of In-System Programmable EEPROM * Endurance: 50,000 Write/Erase Cycles Programming Lock for Flash Program and EEPROM Data Security 1024/2048/4096 Bytes Internal SRAM On Chip Debug Interface (debugWIRE) CAN 2.0A/B with 6 Message Objects - ISO 16845 Certified (1) LIN 2.1 and 1.3 Controller or 8-Bit UART One 12-bit High Speed PSC (Power Stage Controller) (only ATmega16/32/64M1) * Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time * Variable PWM duty Cycle and Frequency * Synchronous Update of all PWM Registers * Auto Stop Function for Emergency Event Peripheral Features - One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode - One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode - One Master/Slave SPI Serial Interface - 10-bit ADC * Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs * Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels * Internal Reference Voltage * Direct Power Supply Voltage Measurement - 10-bit DAC for Variable Voltage Reference (Comparators, ADC) - Four Analog Comparators with Variable Threshold Detection - 100A 3% Current Source (LIN Node Identification) - Interrupt and Wake-up on Pin Change - Programmable Watchdog Timer with Separate On-Chip Oscillator - On-chipTemperature Sensor Special Microcontroller Features - Low Power Idle, Noise Reduction, and Power Down Modes - Power On Reset and Programmable Brown Out Detection - In-System Programmable via SPI Port - High Precision Crystal Oscillator for CAN Operations (16 MHz) See certification on Atmel web site. And note on Section 16.4.3 on page 175. * * * * * * * 8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash ATmega16M1 ATmega32M1 ATmega64M1 ATmega32C1 ATmega64C1 Automotive Preliminary Summary * * 1. 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 - Internal Calibrated RC Oscillator ( 8 MHz) - On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz) * Operating Voltage: 2.7V - 5.5V * Extended Operating Temperature: - -40C to +125C * Core Speed Grade: - 0 - 8MHz @ 2.7 - 4.5V - 0 - 16MHz @ 4.5 - 5.5V ATmega32/64/M1/C1 Product Line-up Part number Flash Size RAM Size EEPROM Size 8-bit Timer 16-bit Timer PSC PWM Outputs Fault Inputs (PSC) PLL 10-bit ADC Channels 10-bit DAC Analog Comparators Current Source CAN LIN/UART On-Chip Temp. Sensor SPI Interface 4 0 No 4 0 10 3 32/64 MHz 11 single 3 Differential Yes 4 Yes Yes Yes Yes Yes 10 3 ATmega32C1 32 Kbyte 2048 bytes 1024 bytes ATmega64C1 64 Kbyte 4096 bytes 2048 bytes ATmega16M1 16 Kbyte 1024 bytes 512 bytes Yes Yes Yes 10 3 ATmega32M1 32 Kbyte 2048 bytes 1024 bytes ATmega64M1 64 Kbyte 4096 bytes 2048 bytes 3 7647DS-AVR-08/08 1. Pin Configurations Figure 1-1. ATmega16/32/64M1 TQFP32/QFN32 (7*7 mm) Package. PB7 (ADC4/PSCOUT0B/SCK/PCINT7) PB6 (ADC7/PSCOUT1B/PCINT6) PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5) PC7 (D2A/AMP2+/PCINT15) ATmega32/64M1 TQFP32/QFN32 PC0(PCINT8/INT3/PSCOUT1A) PD1(PCINT17/PSCIN0/CLKO) PE0 (PCINT24/RESET/OCD) 32 31 30 29 28 27 26 25 PD0 (PCINT16/PSCOUT0A) (PCINT18/PSCIN2/OC1A/MISO_A) PD2 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 (PCINT9/PSCIN1/OC1B/SS_A) PC1 VCC GND (PCINT10/T0/TXCAN) PC2 (PCINT11/T1/RXCAN/ICP1B) PC3 (PCINT0/MISO/PSCOUT2A) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PB4 (AMP0+/PCINT4) PB3 (AMP0-/PCINT3) PC6 (ADC10/ACMP1/PCINT14) AREF(ISRC) AGND AVCC PC5 (ADC9/ACMP3/AMP1+/PCINT13) PC4 (ADC8/ACMPN3/AMP1-/PCINT12) Note: On the engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. 4 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 (PCINT1/MOSI/PSCOUT2B) PB1 (PCINT25/OC0B/XTAL1) PE1 (PCINT26/ADC0/XTAL2) PE2 (PCINT20/ADC1/RXD/RXLIN/ICP1A/SCK_A) PD4 (ADC2/ACMP2/PCINT21) PD5 (ADC3/ACMPN2/INT0/PCINT22) PD6 (ACMP0/PCINT23) PD7 (ADC5/INT1/ACMPN0/PCINT2) PB2 ATmega16/32/64/M1/C1 Figure 1-2. ATmega32/64C1 TQFP32/QFN32 (7*7 mm) Package PB7 (ADC4/SCK/PCINT7) PB6 (ADC7PCINT6) PB5 (ADC6/INT2/ACMPN1/AMP2-/PCINT5) PC7 (D2A/AMP2+/PCINT15) ATmega32/64C1 TQFP32/QFN32 PE0 (PCINT24/RESET/OCD) PD1(PCINT17/CLKO) PC0(PCINT8/INT3) 32 31 30 29 28 27 26 25 PD0 (PCINT16) (PCINT18/OC1A/MISO_A) PD2 (PCINT19/TXD/TXLIN/OC0A/SS/MOSI_A) PD3 (PCINT9/OC1B/SS_A) PC1 VCC GND (PCINT10/T0/TXCAN) PC2 (PCINT11/T1/RXCAN/ICP1B) PC3 (PCINT0/MISO) PB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 PB4 (AMP0+/PCINT4) PB3 (AMP0-/PCINT3) PC6 (ADC10/ACMP1/PCINT14) AREF(ISRC) AGND AVCC PC5 (ADC9/ACMP3/AMP1+/PCINT13) PC4 (ADC8/ACMPN3/AMP1-/PCINT12) Note: On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. (PCINT1/MOSI) PB1 (PCINT25/OC0B/XTAL1) PE1 (PCINT26/ADC0/XTAL2) PE2 (PCINT20/ADC1/RXD/RXLIN/ICP1A/SCK_A) PD4 (ADC2/ACMP2/PCINT21) PD5 (ADC3/ACMPN2/INT0/PCINT22) PD6 (ACMP0/PCINT23) PD7 (ADC5/INT1/ACMPN0/PCINT2) PB2 5 7647DS-AVR-08/08 1.1 Pin Descriptions : Table 1-1. QFN32 Pin Number 5 20 4 19 Pin out description Mnemonic GND AGND VCC AVCC Type Power Power Power Power Name, Function & Alternate Function Ground: 0V reference Analog Ground: 0V reference for analog part Power Supply Analog Power Supply: This is the power supply voltage for analog part For a normal use this pin must be connected. Analog Reference : reference for analog converter . This is the reference voltage of the A/D converter. As output, can be used by external analog ISRC (Current Source Output) MISO (SPI Master In Slave Out) 21 AREF Power 8 PB0 I/O PSCOUT2A(1) (PSC Module 2 Output A) PCINT0 (Pin Change Interrupt 0) MOSI (SPI Master Out Slave In) 9 PB1 I/O PSCOUT2B(1) (PSC Module 2 Output B) PCINT1 (Pin Change Interrupt 1) ADC5 (Analog Input Channel 5 ) INT1 (External Interrupt 1 Input) ACMPN0 (Analog Comparator 0 Negative Input) PCINT2 (Pin Change Interrupt 2) AMP0- (Analog Differential Amplifier 0 Negative Input) PCINT3 (Pin Change Interrupt 3) AMP0+ (Analog Differential Amplifier 0 Positive Input) PCINT4 (Pin Change Interrupt 4) ADC6 (Analog Input Channel 6) INT2 (External Interrupt 2 Input) 16 PB2 I/O 23 24 PB3 PB4 I/O I/O 26 PB5 I/O ACMPN1 (Analog Comparator 1 Negative Input) AMP2- (Analog Differential Amplifier 2 Negative Input) PCINT5 (Pin Change Interrupt 5) ADC7 (Analog Input Channel 7) 27 PB6 I/O PSCOUT1B(1) (PSC Module 1 Output A) PCINT6 (Pin Change Interrupt 6) ADC4 (Analog Input Channel 4) PSCOUT0B(1) (PSC Module 0 Output B) SCK (SPI Clock) PCINT7 (Pin Change Interrupt 7) PSCOUT1A(1) (PSC Module 1 Output A) 28 PB7 I/O 30 PC0 I/O INT3 (External Interrupt 3 Input) PCINT8 (Pin Change Interrupt 8) 6 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 Table 1-1. QFN32 Pin Number Pin out description (Continued) Mnemonic Type Name, Function & Alternate Function PSCIN1 (PSC Digital Input 1) 3 PC1 I/O OC1B (Timer 1 Output Compare B) SS_A (Alternate SPI Slave Select) PCINT9 (Pin Change Interrupt 9) T0 (Timer 0 clock input) 6 PC2 I/O TXCAN (CAN Transmit Output) PCINT10 (Pin Change Interrupt 10) T1 (Timer 1 clock input) RXCAN (CAN Receive Input) ICP1B (Timer 1 input capture alternate B input) PCINT11 (Pin Change Interrupt 11) ADC8 (Analog Input Channel 8) 7 PC3 I/O 17 PC4 I/O AMP1- (Analog Differential Amplifier 1 Negative Input) ACMPN3 (Analog Comparator 3 Negative Input ) PCINT12 (Pin Change Interrupt 12) ADC9 (Analog Input Channel 9) AMP1+ (Analog Differential Amplifier 1 Positive Input) ACMP3 (Analog Comparator 3 Positive Input) PCINT13 (Pin Change Interrupt 13) ADC10 (Analog Input Channel 10) 18 PC5 I/O 22 PC6 I/O ACMP1 (Analog Comparator 1 Positive Input ) PCINT14 (Pin Change Interrupt 14) D2A (DAC output ) 25 PC7 I/O AMP2+ (Analog Differential Amplifier 2 Positive Input) PCINT15 (Pin Change Interrupt 15) PSCOUT0A(1) (PSC Module 0 Output A) PCINT16 (Pin Change Interrupt 16) PSCIN0 (PSC Digital Input 0) CLKO (System Clock Output) PCINT17 (Pin Change Interrupt 17) OC1A (Timer 1 Output Compare A) PSCIN2 (PSC Digital Input 2) MISO_A (Programming & alternate SPI Master In Slave Out) PCINT18 (Pin Change Interrupt 18) TXD (UART Tx data) TXLIN (LIN Transmit Output) 29 PD0 I/O 32 PD1 I/O 1 PD2 I/O 2 PD3 I/O OC0A (Timer 0 Output Compare A) SS (SPI Slave Select) MOSI_A (Programming & alternate Master Out SPI Slave In) PCINT19 (Pin Change Interrupt 19) 7 7647DS-AVR-08/08 Table 1-1. QFN32 Pin Number Pin out description (Continued) Mnemonic Type Name, Function & Alternate Function ADC1 (Analog Input Channel 1) RXD (UART Rx data) 12 PD4 I/O RXLIN (LIN Receive Input) ICP1A (Timer 1 input capture alternate A input) SCK_A (Programming & alternate SPI Clock) PCINT20 (Pin Change Interrupt 20) ADC2 (Analog Input Channel 2) 13 PD5 I/O ACMP2 (Analog Comparator 2 Positive Input ) PCINT21 (Pin Change Interrupt 21) ADC3 (Analog Input Channel 3 ) ACMPN2 (Analog Comparator 2 Negative Input) INT0 (External Interrupt 0 Input) PCINT22 (Pin Change Interrupt 22) ACMP0 (Analog Comparator 0 Positive Input ) PCINT23 (Pin Change Interrupt 23) RESET (Reset Input) OCD (On Chip Debug I/O) PCINT24 (Pin Change Interrupt 24) XTAL1 (XTAL Input) 14 PD6 I/O 15 PD7 I/O 31 PE0 I/O or I 10 PE1 I/O OC0B (Timer 0 Output Compare B) PCINT25 (Pin Change Interrupt 25) XTAL2 (XTAL Output) 11 PE2 I/O ADC0 (Analog Input Channel 0) PCINT26 (Pin Change Interrupt 26) Note: 1. Only for ATmega32/64M1. 2. On the first engineering samples (Parts marked AT90PWM324), the ACMPN3 alternate function is not located on PC4. It is located on PE2. 2. Overview The ATmega16/32/64/M1/C1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega16/32/64/M1/C1 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 8 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 2.1 Block Diagram Figure 2-1. Block Diagram Data Bus 8-bit Flash Program Memory Program Counter Status and Control Interrupt Unit SPI Unit Instruction Register 32 x 8 General Purpose Registrers Watchdog Timer 4 Analog Comparators Instruction Decoder Indirect Addressing Direct Addressing ALU HW LIN/UART Control Lines Timer 0 Timer 1 Data SRAM ADC EEPROM DAC I/O Lines PSC Current Source CAN The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega16/32/64/M1/C1 provides the following features: 16K/32K/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/1024/2048 bytes EEPROM, 1024/2048/4096 bytes SRAM, 27 general purpose I/O lines, 32 general purpose working registers, one Motor Power Stage Controller, two flexible Timer/Counters with compare modes and PWM, one UART with HW LIN, an 11-channel 10-bit ADC with two differential input stages with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Individual Oscillator, an SPI serial port, an On-chip Debug system and four software selectable power saving modes. 9 7647DS-AVR-08/08 The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports, CAN, LIN/UART and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel's high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega16/32/64/M1/C1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega16/32/64/M1/C1 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Automotive Quality Grade The ATmega16/32/64/M1/C1 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATmega16/32/64/M1/C1 have been verified during regular product qualification as per AEC-Q100 grade 1. As indicated in the ordering information paragraph, the products are available in only one temperature grade. Table 2-1. Temperature -40 ; +125 Temperature Grade Identification for Automotive Products Temperature Identifier Z Comments Full AutomotiveTemperature Range 2.3 2.3.1 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 10 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 2.3.3 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega16/32/64/M1/C1 as listed on page 68. 2.3.4 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega16/32/64/M1/C1 as listed on page 72. 2.3.5 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega16/32/64/M1/C1 as listed on page 75. 2.3.6 Port E (PE2..0) RESET/ XTAL1/ XTAL2 Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins of Port E. If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 7-1 on page 46. Shorter pulses are not guaranteed to generate a Reset. Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier. 11 7647DS-AVR-08/08 The various special features of Port E are elaborated in "Alternate Functions of Port E" on page 78 and "Clock Systems and their Distribution" on page 29. 2.3.7 AVCC AVCC is the supply voltage pin for the A/D Converter, D/A Converter, Current source. It should be externally connected to VCC, even if the ADC, DAC are not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.8 AREF This is the analog reference pin for the A/D Converter. 2.4 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 12 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 3. Register Summary Address (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF) Name Reserved Reserved Reserved Reserved Reserved CANMSG CANSTMPH CANSTMPL CANIDM1 CANIDM2 CANIDM3 CANIDM4 CANIDT1 CANIDT2 CANIDT3 CANIDT4 CANCDMOB CANSTMOB CANPAGE CANHPMOB CANREC CANTEC CANTTCH CANTTCL CANTIMH CANTIML CANTCON CANBT3 CANBT2 CANBT1 CANSIT1 CANSIT2 CANIE1 CANIE2 CANEN1 CANEN2 CANGIE CANGIT CANGSTA CANGCON Reserved Reserved Reserved Reserved Reserved LINDAT LINSEL LINIDR LINDLR LINBRRH LINBRRL LINBTR LINERR LINENIR LINSIR LINCR Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Bit 7 - - - - - MSG 7 TIMSTM15 TIMSTM7 IDMSK28 IDMSK20 IDMSK12 IDMSK4 IDT28 IDT20 IDT12 IDT4 CONMOB1 DLCW MOBNB3 HPMOB3 REC7 TEC7 TIMTTC15 TIMTTC7 CANTIM15 CANTIM7 TPRSC7 - - - - - - - - - ENIT CANIT - ABRQ - - - - - LDATA7 - LP1 LTXDL3 - LDIV7 LDISR LABORT - LIDST2 LSWRES - - - - - - - - - Bit 6 - - - - - MSG 6 TIMSTM14 TIMSTM6 IDMSK27 IDMSK19 IDMSK11 IDMSK3 IDT27 IDT19 IDT11 IDT3 CONMOB0 TXOK MOBNB2 HPMOB2 REC6 TEC6 TIMTTC14 TIMTTC6 CANTIM14 CANTIM6 TPRSC6 PHS22 SJW1 BRP5 - - - - - - ENBOFF BOFFIT OVRG OVRQ - - - - - LDATA6 - LP0 LTXDL2 - LDIV6 - LTOERR - LIDST1 LIN13 - - - - - - - - - Bit 5 - - - - - MSG 5 TIMSTM13 TIMSTM5 IDMSK26 IDMSK18 IDMSK10 IDMSK2 IDT26 IDT18 IDT10 IDT2 RPLV RXOK MOBNB1 HPMOB1 REC5 TEC5 TIMTTC13 TIMTTC5 CANTIM13 CANTIM5 TPRSC5 PHS21 SJW0 BRP4 - SIT5 - IEMOB5 - ENMOB5 ENRX OVRTIM - TTC - - - - - LDATA5 - LID5 / LDL1 LTXDL1 - LDIV5 LBT5 LOVERR - LIDST0 LCONF1 - - - - - - - - - Bit 4 - - - - - MSG 4 TIMSTM12 TIMSTM4 IDMSK25 IDMSK17 IDMSK9 IDMSK1 IDT25 IDT17 IDT9 IDT1 IDE BERR MOBNB0 HPMOB0 REC4 TEC4 TIMTTC12 TIMTTC4 CANTIM12 CANTIM4 TPRSC4 PHS20 - BRP3 - SIT4 - IEMOB4 - ENMOB4 ENTX BXOK TXBSY SYNTTC - - - - - LDATA4 - LID4 / LDL0 LTXDL0 - LDIV4 LBT4 LFERR - LBUSY LCONF0 - - - - - - - - - Bit 3 - - - - - MSG 3 TIMSTM11 TIMSTM3 IDMSK24 IDMSK16 IDMSK8 IDMSK0 IDT24 IDT16 IDT8 IDT0 DLC3 SERR AINC CGP3 REC3 TEC3 TIMTTC11 TIMTTC3 CANTIM11 CANTIM3 TPRSC3 PHS12 PRS2 BRP2 - SIT3 - IEMOB3 - ENMOB3 ENERR SERG RXBSY LISTEN - - - - - LDATA3 /LAINC LID3 LRXDL3 LDIV11 LDIV3 LBT3 LSERR LENERR LERR LENA - - - - - - - - - Bit 2 - - - - - MSG 2 TIMSTM10 TIMSTM2 IDMSK23 IDMSK15 IDMSK7 RTRMSK IDT23 IDT15 IDT7 RTRTAG DLC2 CERR INDX2 CGP2 REC2 TEC2 TIMTTC10 TIMTTC2 CANTIM10 CANTIM2 TPRSC2 PHS11 PRS1 BRP1 - SIT2 - IEMOB2 - ENMOB2 ENBX CERG ENFG TEST - - - - - LDATA2 LINDX2 LID2 LRXDL2 LDIV10 LDIV2 LBT2 LPERR LENIDOK LIDOK LCMD2 - - - - - - - - - Bit 1 - - - - - MSG 1 TIMSTM9 TIMSTM1 IDMSK22 IDMSK14 IDMSK6 - IDT22 IDT14 IDT6 RB1TAG DLC1 FERR INDX1 CGP1 REC1 TEC1 TIMTTC9 TIMTTC1 CANTIM9 CANTIM1 TRPSC1 PHS10 PRS0 BRP0 - SIT1 - IEMOB1 - ENMOB1 ENERG FERG BOFF ENA/STB - - - - - LDATA1 LINDX1 LID1 LRXDL1 LDIV9 LDIV1 LBT1 LCERR LENTXOK LTXOK LCMD1 - - - - - - - - - Bit 0 - - - - - MSG 0 TIMSTM8 TIMSTM0 IDMSK21 IDMSK13 IDMSK5 IDEMSK IDT21 IDT13 IDT5 RB0TAG DLC0 AERR INDX0 CGP0 REC0 TEC0 TIMTTC8 TIMTTC0 CANTIM8 CANTIM0 TPRSC0 SMP - - - SIT0 - IEMOB0 - ENMOB0 ENOVRT AERG ERRP SWRES - - - - - LDATA0 LINDX0 LID0 LRXDL0 LDIV8 LDIV0 LBT0 LBERR LENRXOK LRXOK LCMD0 - - - - - - - - - Page page 199 page 199 page 199 page 198 page 198 page 198 page 198 page 196 page 196 page 196 page 196 page 195 page 194 page 194 page 193 page 193 page 193 page 193 page 193 page 193 page 193 page 192 page 192 page 191 page 190 page 190 page 190 page 190 page 190 page 189 page 189 page 188 page 187 page 186 page 185 page 226 page 226 page 225 page 224 page 224 page 224 page 224 page 223 page 222 page 221 page 220 13 7647DS-AVR-08/08 Address (0xBE) (0xBD) (0xBC)(5) (0xBB)(5) (0xBA)(5) (0xB9)(5) (0xB8)(5) (0xB7)(5) (0xB6)(5) (0xB5)(5) (0xB4)(5) (0xB3)(5) (0xB2)(5) (0xB1)(5) (0xB0)(5) (0xAF)(5) (0xAE)(5) (0xAD)(5) (0xAC)(5) (0xAB)(5) (0xAA)(5) (0xA9)(5) (0xA8)(5) (0xA7)(5) (0xA6)(5) (0xA5)(5) (0xA4)(5) (0xA3)(5) (0xA2)(5) (0xA1)(5) (0xA0)(5) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D) Name Reserved Reserved PIFR PIM PMIC2 PMIC1 PMIC0 PCTL POC PCNF PSYNC POCR_RBH POCR_RBL POCR2SBH POCR2SBL POCR2RAH POCR2RAL POCR2SAH POCR2SAL POCR1SBH POCR1SBL POCR1RAH POCR1RAL POCR1SAH POCR1SAL POCR0SBH POCR0SBL POCR0RAH POCR0RAL POCR0SAH POCR0SAL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved AC3CON AC2CON AC1CON AC0CON Reserved DACH DACL DACON Reserved Reserved Reserved Reserved OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 Reserved Bit 7 - - - - POVEN2 POVEN1 POVEN0 PPRE1 - - - - POCR_RB7 - POCR2SB7 - POCR2RA7 - POCR2SA7 - POCR1SB7 - POCR1RA7 - POCR1SA7 - POCR0SB7 - POCR0RA7 - POCR0SA7 - - - - - - - - AC3EN AC2EN AC1EN AC0EN - - / DAC9 DAC7 / DAC1 DAATE - - - - OCR1B15 OCR1B7 OCR1A15 OCR1A7 ICR115 ICR17 TCNT115 TCNT17 - FOC1A ICNC1 COM1A1 - ADC7D - Bit 6 - - - - PISEL2 PISEL1 PISEL0 PPRE0 - - - - POCR_RB6 - POCR2SB6 - POCR2RA6 - POCR2SA6 - POCR1SB6 - POCR1RA6 - POCR1SA6 - POCR0SB6 - POCR0RA6 - POCR0SA6 - - - - - - - - AC3IE AC2IE AC1IE AC0IE - - / DAC8 DAC6 /DAC0 DATS2 - - - - OCR1B14 OCR1B6 OCR1A14 OCR1A6 ICR114 ICR16 TCNT114 TCNT16 - FOC1B ICES1 COM1A0 AMP2PD ADC6D - Bit 5 - - - - PELEV2 PELEV1 PELEV0 PCLKSEL POEN2B PULOCK PSYNC21 - POCR_RB5 - POCR2SB5 - POCR2RA5 - POCR2SA5 - POCR1SB5 - POCR1RA5 - POCR1SA5 - POCR0SB5 - POCR0RA5 - POCR0SA5 - - - - - - - - AC3IS1 AC2IS1 AC1IS1 AC0IS1 - - / DAC7 DAC5 / DATS1 - - - - OCR1B13 OCR1B5 OCR1A13 OCR1A5 ICR113 ICR15 TCNT113 TCNT15 - - - COM1B1 ACMP0D ADC5D - Bit 4 - - - - PFLTE2 PFLTE1 PFLTE0 - POEN2A PMODE PSYNC20 - POCR_RB4 - POCR2SB4 - POCR2RA4 - POCR2SA4 - POCR1SB4 - POCR1RA4 - POCR1SA4 - POCR0SB4 - POCR0RA4 - POCR0SA4 - - - - - - - - AC3IS0 AC2IS0 AC1IS0 AC0IS0 - - / DAC6 DAC4 / DATS0 - - - - OCR1B12 OCR1B4 OCR1A12 OCR1A4 ICR112 ICR14 TCNT112 TCNT14 - - WGM13 COM1B0 AMP0PD ADC4D - Bit 3 - - PEV2 PEVE2 PAOC2 PAOC1 PAOC0 - POEN1B POPB PSYNC11 POCR_RB11 POCR_RB3 POCR2SB11 POCR2SB3 POCR2RA11 POCR2RA3 POCR2SA11 POCR2SA3 POCR1SB11 POCR1SB3 POCR1RA11 POCR1RA3 POCR1SA11 POCR1SA3 POCR0SB11 POCR0SB3 POCR0RA11 POCR0RA3 POCR0SA11 POCR0SA3 - - - - - - - - - - AC1ICE ACCKSEL - - / DAC5 DAC3 / - - - - - OCR1B11 OCR1B3 OCR1A11 OCR1A3 ICR111 ICR13 TCNT111 TCNT13 - - WGM12 - AMP0ND ADC3D - Bit 2 - - PEV1 PEVE1 PRFM22 PRFM12 PRFM02 - POEN1A POPA PSYNC10 POCR_RB10 POCR_RB2 POCR2SB10 POCR2SB2 POCR2RA10 POCR2RA2 POCR2SA10 POCR2SA2 POCR1SB10 POCR1SB2 POCR1RA10 POCR1RA2 POCR1SA10 POCR1SA2 POCR0SB10 POCR0SB2 POCR0RA10 POCR0RA2 POCR0SA10 POCR0SA2 - - - - - - - - AC3M2 AC2M2 AC1M2 AC0M2 - - / DAC4 DAC2 / DALA - - - - OCR1B10 OCR1B2 OCR1A10 OCR1A2 ICR110 ICR12 TCNT110 TCNT12 - - CS12 - ADC10D ADC2D - Bit 1 - - PEV0 PEVE0 PRFM21 PRFM11 PRFM01 PCCYC POEN0B - PSYNC01 POCR_RB9 POCR_RB1 POCR2SB9 POCR2SB1 POCR2RA9 POCR2RA1 POCR2SA9 POCR2SA1 POCR1SB9 POCR1SB1 POCR1RA9 POCR1RA1 POCR1SA9 POCR1SA1 POCR0SB9 POCR0SB1 POCR0RA9 POCR0RA1 POCR0SA9 POCR0SA1 - - - - - - - - AC3M1 AC2M1 AC1M1 AC0M1 - DAC9 / DAC3 DAC1 / DAOE - - - - OCR1B9 OCR1B1 OCR1A9 OCR1A1 ICR19 ICR11 TCNT19 TCNT11 - - CS11 WGM11 ADC9D ADC1D - Bit 0 - - PEOP PEOPE PRFM20 PRFM10 PRFM00 PRUN POEN0A - PSYNC00 POCR_RB8 POCR_RB0 POCR2SB8 POCR2SB0 POCR2RA8 POCR2RA0 POCR2SA8 POCR2SA0 POCR1SB8 POCR1SB0 POCR1RA8 POCR1RA0 POCR1SA8 POCR1SA0 POCR0SB8 POCR0SB0 POCR0RA8 POCR0RA0 POCR0SA8 POCR0SA0 - - - - - - - - AC3M0 AC2M0 AC1M0 AC0M0 - DAC8 / DAC2 DAC0 / DAEN - - - - OCR1B8 OCR1B0 OCR1A8 OCR1A0 ICR18 ICR10 TCNT18 TCNT10 - - CS10 WGM10 ADC8D ADC0D - Page page 155 page 155 page 154 page 154 page 154 page 153 page 149 page 152 page 150 page 152 page 152 page 152 page 152 page 151 page 151 page 151 page 151 page 152 page 152 page 151 page 151 page 151 page 151 page 152 page 152 page 151 page 151 page 151 page 151 page 263 page 263 page 262 page 261 page 270 page 270 page 269 page 131 page 132 page 131 page 131 page 133 page 133 page 131 page 131 page 131 page 130 page 127 page 246 page 246 14 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 Address (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) Name ADMUX ADCSRB ADCSRA ADCH ADCL AMP2CSR AMP1CSR AMP0CSR Reserved Reserved Reserved Reserved Reserved TIMSK1 TIMSK0 PCMSK3 PCMSK2 PCMSK1 PCMSK0 EICRA PCICR Reserved OSCCAL Reserved PRR Reserved Reserved CLKPR WDTCSR SREG SPH SPL Reserved Reserved Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR MSMCR MONDR ACSR Reserved SPDR SPSR SPCR Reserved Reserved PLLCSR OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR PCIFR Bit 7 REFS1 ADHSM ADEN - / ADC9 ADC7 / ADC1 AMP2EN AMP1EN AMP0EN - - - - - - - - PCINT23 PCINT15 PCINT7 ISC31 - - - - - - - CLKPCE WDIF I SP15 SP7 - - - - - SPMIE - SPIPS - - Bit 6 REFS0 ISRCEN ADSC - / ADC8 ADC6 / ADC0 AMP2IS AMP1IS AMP0IS - - - - - - - - PCINT22 PCINT14 PCINT6 ISC30 - - CAL6 - PRCAN - - - WDIE T SP14 SP6 - - - - - RWWSB - - - - Bit 5 ADLAR AREFEN ADATE - / ADC7 ADC5 / AMP2G1 AMP1G1 AMP0G1 - - - - - ICIE1 - - PCINT21 PCINT13 PCINT5 ISC21 - - CAL5 - PRPSC - - - WDP3 H SP13 SP5 - - - - - SIGRD - - - - Bit 4 - - ADIF - / ADC6 ADC4 / AMP2G0 AMP1G0 AMP0G0 - - - - - - - - PCINT20 PCINT12 PCINT4 ISC20 - - CAL4 - PRTIM1 - - - WDCE S SP12 SP4 - - - - - RWWSRE - PUD - - Bit 3 MUX3 ADTS3 ADIE - / ADC5 ADC3 / AMPCMP2 AMPCMP1 AMPCMP0 - - - - - - - - PCINT19 PCINT11 PCINT3 ISC11 PCIE3 - CAL3 - PRTIM0 - - CLKPS3 WDE V SP11 SP3 - - - - - BLBSET - - WDRF SM2 Bit 2 MUX2 ADTS2 ADPS2 - / ADC4 ADC2 / AMP2TS2 AMP1TS2 AMP0TS2 - - - - - OCIE1B OCIE0B PCINT26 PCINT18 PCINT10 PCINT2 ISC10 PCIE2 - CAL2 - PRSPI - - CLKPS2 WDP2 N SP10 SP2 - - - - - PGWRT - - BORF SM1 Bit 1 MUX1 ADTS1 ADPS1 ADC9 / ADC3 ADC1 / AMP2TS1 AMP1TS1 AMP0TS1 - - - - - OCIE1A OCIE0A PCINT25 PCINT17 PCINT9 PCINT1 ISC01 PCIE1 - CAL1 - PRLIN - - CLKPS1 WDP1 Z SP9 SP1 - - - - - PGERS - IVSEL EXTRF SM0 Bit 0 MUX0 ADTS0 ADPS0 ADC8 / ADC2 ADC0 / AMP2TS0 AMP1TS0 AMP0TS0 - - - - - TOIE1 TOIE0 PCINT24 PCINT16 PCINT8 PCINT0 ISC00 PCIE0 - CAL0 - PRADC - - CLKPS0 WDP0 C SP8 SP0 - - - - - SPMEN - IVCE PORF SE Page page 242 page 244 page 243 page 245 page 245 page 252 page 252 page 251 page 133 page 105 page 85 page 86 page 86 page 86 page 83 page 84 page 33 page 42 page 38 page 53 page 14 page 16 page 16 page 281 page 59 & page 68 page 49 page 40 reserved reserved Monitor Stop Mode Control Register Monitor Data Register AC3IF - SPD7 SPIF SPIE - - OCR0B7 OCR0A7 TCNT07 FOC0A COM0A1 TSM - EEAR7 EEDR7 - GPIOR07 - - - AC2IF - SPD6 WCOL SPE - - OCR0B6 OCR0A6 TCNT06 FOC0B COM0A0 ICPSEL1 - EEAR6 EEDR6 - GPIOR06 - - - AC1IF - SPD5 - DORD - - OCR0B5 OCR0A5 TCNT05 - COM0B1 - - EEAR5 EEDR5 - GPIOR05 - - - AC0IF - SPD4 - MSTR - - OCR0B4 OCR0A4 TCNT04 - COM0B0 - - EEAR4 EEDR4 - GPIOR04 - - - AC3O - SPD3 - CPOL - - OCR0B3 OCR0A3 TCNT03 WGM02 - - - EEAR3 EEDR3 EERIE GPIOR03 INT3 INTF3 PCIF3 AC2O - SPD2 - CPHA - - PLLF OCR0B2 OCR0A2 TCNT02 CS02 - - - EEAR2 EEDR2 EEMWE GPIOR02 INT2 INTF2 PCIF2 AC1O - SPD1 - SPR1 - - PLLE OCR0B1 OCR0A1 TCNT01 CS01 WGM01 - EEAR9 EEAR1 EEDR1 EEWE GPIOR01 INT1 INTF1 PCIF1 AC0O - SPD0 SPI2X SPR0 - - PLOCK OCR0B0 OCR0A0 TCNT00 CS00 WGM00 PSRSYNC EEAR8 EEAR0 EEDR0 EERE GPIOR00 INT0 INTF0 PCIF0 page 265 page 165 page 164 page 163 page 36 page 105 page 105 page 105 page 103 page 101 page 88 page 23 page 23 page 23 page 23 page 28 page 83 page 84 page 85 15 7647DS-AVR-08/08 Address 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20) Name GPIOR2 GPIOR1 Reserved Reserved TIFR1 TIFR0 Reserved Reserved Reserved Reserved Reserved Reserved PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB Reserved Reserved Reserved Bit 7 GPIOR27 GPIOR17 - - - - - - - - - - - - - PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 - - - Bit 6 GPIOR26 GPIOR16 - - - - - - - - - - - - - PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 - - - Bit 5 GPIOR25 GPIOR15 - - ICF1 - - - - - - - - - - PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 - - - Bit 4 GPIOR24 GPIOR14 - - - - - - - - - - - - - PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 - - - Bit 3 GPIOR23 GPIOR13 - - - - - - - - - - - - - PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 - - - Bit 2 GPIOR22 GPIOR12 - - OCF1B OCF0B - - - - - - PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 - - - Bit 1 GPIOR21 GPIOR11 - - OCF1A OCF0A - - - - - - PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 - - - Bit 0 GPIOR20 GPIOR10 - - TOV1 TOV0 - - - - - - PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 - - - Page page 28 page 28 page 134 page 106 page 81 page 81 page 81 page 80 page 80 page 81 page 80 page 80 page 80 page 80 page 80 page 80 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega16/32/64/M1/C1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. 5. These registers are only available on ATmega32/64M1. For other products described in this datasheet, these locations are reserved. 16 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 4. Instruction Set Summary Mnemonics ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP(*) RCALL ICALL CALL(*) RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k Operands Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Description Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers One's Complement Two's Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned BRANCH INSTRUCTIONS Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Operation Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 Flags Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None #Clocks 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 ARITHMETIC AND LOGIC INSTRUCTIONS 17 7647DS-AVR-08/08 Mnemonics BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH Operands k k P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Description Branch if Interrupt Enabled Branch if Interrupt Disabled Operation if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Flags None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None #Clocks 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 BIT AND BIT-TEST INSTRUCTIONS Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG DATA TRANSFER INSTRUCTIONS Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack 18 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 Mnemonics POP NOP SLEEP WDR BREAK Operands Rd Description Pop Register from Stack Operation Rd STACK Flags None None #Clocks 2 1 1 1 N/A MCU CONTROL INSTRUCTIONS No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None Note: 1. These Instructions are only available in "16K and 32K parts" 19 7647DS-AVR-08/08 5. Errata 5.1 5.1.1 Errata Summary ATmega32M1/C1 Rev. C (Mask Revision) * The AMPCMPx bits return 0 5.1.2 ATmega32M1/C1 Rev. B (Mask Revision) * The AMPCMPx bits return 0 * No comparison when amplifier is used as comparator input and ADC input * CRC calculation of diagnostic frames in LIN 2.x. * Wrong TSOFFSET manufacturing calibration value * PD0-PD3 set to outputs and PD4 pulled down following power-on with external reset active. 5.1.3 ATmega32M1/C1 Rev. A (Mask Revision) * Inopportune reset of the CANIDM registers. * The AMPCMPx bits return 0 * No comparison when amplifier is used as comparator input and ADC input * CRC calculation of diagnostic frames in LIN 2.x. * PD0-PD3 set to outputs and PD4 pulled down following power-on with external reset active. 5.1.4 Errata Description 1. Inopportune reset of the CANIDM registers After the reception of a CAN frame in a MOb, the ID mask registers are reset. Problem fix / workaround Before enabling a MOb in reception, re-initialize the ID mask registers - CANIDM[4..1]. 2. The AMPCMPx bits return 0 When they are read the AMPCMPx bits in AMPxCSR registers return 0. Problem fix / workaround If the reading of the AMPCMPx bits is required, store the AMPCMPx value in a variable in memory before writing in the AMPxCSR register and read the variable when necessary. 3. No comparison when amplifier is used as comparator input and ADC input When it is selected as ADC input, an amplifier receives no clock signal when the ADC is stopped. In that case, if the amplifier is also used as comparator input, no analog signal is propagated and no comparison is done. Problem fix / workaround Select another ADC channel rather than the working amplified channel. 4. CRC calculation of diagnostic frames in LIN 2.x. Diagnostic frames of LIN 2.x use "classic checksum" calculation. Unfortunately, the setting of the checksum model is enabled when the HEADER is transmitted/received. Usually, in LIN 2.x the LIN/UART controller is initialized to process "enhanced checksums" and a slave task does not know what kind of frame it will work on before checking the ID. Problem fix / workaround This workaround is to be implemented only in case of transmission/reception of diagnostics frames. 20 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 a. Slave task of master node: Before enabling the HEADER, the master must set the appropriate LIN13 bit value in LINCR register. b. For slaves nodes, the workaround is in 2 parts: - Before enabling the RESPONSE, use the following function: void lin_wa_head(void) { unsigned char temp; temp = LINBTR; LINCR = 0x00; // It is not a RESET ! LINBTR = (1< void lin_wa_tail(void) { LINCR = 0x00; // It is not a RESET ! LINBTR = 0x00; LINCR = (0< 5. Wrong TSOFFSET manufacturing calibration value. Erroneous value of TSOFFSET programmed in signature byte. (TSOFFSET was introduced from REVB silicon). Problem fix / workaround To identify RevB with wrong TSOFFSET value, check device signature byte at address 0X3F if value is not 0X42 (Ascii code `B') then use the following formula. TS_OFFSET(True) = (150*(1-TS_GAIN))+TS_OFFSET. 6. PD0-PD3 set to outputs and PD4 pulled down following power-on with external reset active. At power-on with the external reset signal active the four I/O lines PD0-PD3 may be forced into an output state. Normally these lines should be in an input state. PD4 may be pulled down with internal 220 kOhm resistor. Following release of the reset line (whatever is the startup time) with the clock running the I/Os PD0-PD4 will adopt their intended input state. Problem fix / workaround None 21 7647DS-AVR-08/08 6. Ordering Information Figure 6-1. ATmega32M1 engineering samples delivery only. Automotive qualification not yet fully completed. PSC No No No No Yes Yes Yes Yes Power Supply 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V 2.7 - 5.5V Ordering Code MEGA32C1-15AZ MEGA32C1-15MZ MEGA32C1-ESAZ MEGA32C1-ESMZ MEGA32M1-15AZ MEGA32M1-15MZ MEGA32M1-ESAZ MEGA32M1-ESMZ Package MA PV MA PV MA PV MA PV Operation Range -40C to 125C -40C to 125C Engineering Samples Engineering Samples -40C to 125C -40C to 125C Engineering Samples Engineering Samples Memory Size 32K 32K 32K 32K 32K 32K 32K 32K Note: All packages are Pb free, fully LHF 22 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 7. Package Information Package Type MA, 32 - Lead, 7x7 mm Body Size, 1.0 mm Body Thickness 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) PV, 32-Lead, 5.0x5.0 mm Body, 0.50 mm Pitch Quad Flat No Lead Package (QFN) MA PV 23 7647DS-AVR-08/08 7.1 TQFP32 24 ATmega16/32/64/M1/C1 7647DS-AVR-08/08 ATmega16/32/64/M1/C1 7.2 QFN32 25 7647DS-AVR-08/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) 2008 Atmel Corporation. All rights reserved. Atmel (R), logo and combinations thereof, AVR (R) and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 7647DS-AVR-08/08 |
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